Advanced Wafer/Package Assembly Development Integrator

Job Title

Advanced Wafer/Package Assembly Development Integrator

Role Summary

The Development Integrator manages execution of critical development silicon at the platform level for wafer and package assembly flows supporting Intel Foundry customers. The role coordinates integration, factory, and cross-site teams to deliver engineering, test vehicle, and experimental lots to schedule and quality targets.

Primary responsibilities include technical integration across wafer/package flows, schedule and lot management, risk communication, and driving resolution of process or design gaps.

Experience Level

Mid-level. Typical background per posting: Master's degree plus ~5 years relevant experience or PhD plus ~3 years in wafer/package assembly and integration.

Responsibilities

The integrator ensures on-schedule execution of development lots and coordinates across design, integration, and manufacturing teams.

• Manage execution and delivery of development, test vehicle, engineering, and experimental lots through wafer and package assembly flows.
• Lead cross-functional and cross-site integration efforts; drive decisions to resolve technical gaps and enable technology.
• Own virtual line baseline material planning (ENG, TD, DOE) and weekly build forecasts; align lot starts.
• Maintain and communicate upstream/downstream schedules and lot status to stakeholders and customers.
• Partner with design integration, wafer/package integration, module and operations teams to meet PADK milestones.
• Assess design risk, support process integration, and execute FMEAs.
• Support manufacturing operations understanding, sort/test flows, and substrate assembly/test requirements.

Requirements

Key technical and professional requirements. Degree specifics are listed in the Education Requirements section below.

Must-have:

• Practical experience in wafer and package assembly and integration workflows.
• Proven ability to lead cross-site or cross-functional technical teams and influence stakeholders to meet development schedules.
• Experience managing lot flow and build forecasts, including lot tracking and schedule communication.
• Foundational knowledge of materials interactions at wafer/package level (organics/inorganics, CTE) and process-control parameters.
• Familiarity with manufacturing systems, mid-section/wafer and package assembly flow, and sort/test processes.
• Strong communication, problem-solving, and collaboration skills; tolerance for ambiguity in fast-changing environments.

Nice-to-have / Preferred:

• Experience leading virtual factory/site collaboration and mentoring others on technical issue resolution.
• Ability to build and maintain program schedules and Gantt timelines in Excel or scheduling tools.
• Understanding of tool sharing, back-qualification, and determining minimum technology requirements.

Education Requirements

Must have either: a Master's degree in a relevant engineering or science field (Electrical, Mechanical, Chemical, Materials Engineering or related sciences) plus 5+ years' experience in wafer/package assembly; or a PhD in a relevant field plus 3+ years' experience in wafer/package assembly.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.