Advanced Digital Nodes Yield Diagnostics Engineer

Job Title

Advanced Digital Nodes Yield Diagnostics Engineer

Role Summary

Lead yield diagnostics and optimization for advanced-node digital ASIC products from New Product Introduction through high-volume manufacturing. Work across design, test, foundry, and operations to identify yield limiters and implement data-driven corrective actions.

Primary focus includes scan diagnostics, electrical/failure analysis, statistical modeling, and automation to improve silicon quality and manufacturing efficiency.

Experience Level

Mid-level. The posting references multi-year experience ranges depending on degree (see Education Requirements for details).

Responsibilities

Key responsibilities include:

• Lead yield diagnostics across wafer sort, final test, and system-level validation.
• Perform root-cause analysis using scan diagnostics, electrical data, and statistical techniques.
• Collaborate with Design, DFT, Test Engineering, Foundry, and Operations to resolve yield issues and implement corrective actions.
• Define and execute yield monitoring strategies, KPIs, dashboards, and automated reporting.
• Develop and improve data infrastructure, automation, and diagnostic methodologies.
• Drive continuous yield improvement during ramp to high-volume manufacturing.

Requirements

Must-have technical skills and experience:

• Experience in yield analytics, diagnostics, and semiconductor data analysis in a manufacturing environment.
• Proven track record of driving yield improvement in high-volume manufacturing.
• Knowledge of digital design architecture and DFT methodologies (scan, ATPG).
• Familiarity with test flows including ATE and SLT.
• Strong statistical and large-scale data analysis skills.
• Effective cross-functional collaboration and problem-solving skills.

Nice-to-have:

• Hands-on experience with scan diagnosis tools for volume yield analysis.
• Experience applying ML/AI techniques to yield analytics or diagnostics.
• Experience with advanced-node process yield ramp activities.

Education Requirements

Preferred: M.S. or Ph.D. in Electrical Engineering or a related field (posting cites M.S./Ph.D. with 5+ years of relevant industry experience). Minimum options listed: Bachelor's in Science or Engineering with 4+ years relevant ASIC design/verification/validation/integration experience; OR Master's with 3+ years; OR Ph.D. with 2+ years. Fields: Electrical Engineering, other engineering or related technical disciplines. Equivalent industry experience is accepted per the listed minimums.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.