SiFive RISC-V Processor Design Engineer Jobs

SiFive sells the RISC-V cores that other companies build products around, which makes its design roles unusual. You work on IP that ships inside hundreds of other chips rather than a single end product, so the microarchitecture decisions you make show up across automotive, edge AI, IoT, and data center parts.

The company was founded by three of the people who created RISC-V: Krste Asanović, Yunsup Lee, and Andrew Waterman. It has grown into the largest commercial RISC-V IP vendor, licensing customizable cores to semiconductor companies worldwide.

SiFive RISC-V processor design engineer jobs span core microarchitecture, vector extension development, coherent interconnect design, and physical implementation. Most teams write in Chisel, the Scala-embedded hardware construction language SiFive uses for much of its processor IP, though some work is still SystemVerilog. Expect to spend real time in CPU performance modeling and RISC-V ISA microarchitecture, not just RTL entry.

The catalog splits three ways. The Performance P-series covers high-end application processors like the P550. The Essential E-series covers embedded microcontrollers. The Intelligence X-series, including the X280, handles vector and AI workloads. Which family you join shapes whether you are optimizing a Linux-capable application core or a real-time embedded core.

Because customers specify their own microarchitecture, cache, and ISA extension customizations, engineers here see the breadth of how RISC-V gets deployed. That is a draw for architects who want their work to reach AI chip design teams and automotive silicon alike rather than one product line.

Hiring runs out of the Santa Clara, CA headquarters plus offices in Austin, TX, Hsinchu, Taiwan, Seoul, South Korea, and Bengaluru, India. Compensation for RISC-V CPU design work in the US generally tracks the higher end of the semiconductor band; the salary guide has current ranges by level and location.

If you have shipped a RISC-V core or done vector extension work, SiFive openings sit near other RISC-V and AI processor roles on the board, including Tenstorrent and dedicated RISC-V CPU design engineer jobs. Save a search on SemiDesignJobs and you will get an email when a matching SiFive role opens.

FAQ

What RISC-V core families does SiFive design

SiFive designs the Essential E-series embedded microcontrollers, the S-series and U-series application-class cores, the Performance P-series for high-performance application processors, and the Intelligence X-series for vector and AI workloads. It also does custom work for customers who need a differentiated RISC-V implementation.

What HDL does SiFive use for RISC-V processor design

Much of SiFive's processor IP is built in Chisel, a hardware construction language embedded in Scala. Familiarity with Chisel, or a clear willingness to pick it up, matters for design engineers joining the core teams. Some blocks still use SystemVerilog.

What markets is SiFive targeting with its RISC-V IP

SiFive targets automotive ADAS and domain controllers, AI edge inference, IoT microcontrollers, and high-performance data center accelerators. The P550 and Intelligence X280 cores in particular aim at high-performance AI and automotive applications.