Samsung Foundry Design Enablement Engineer Jobs
Samsung Foundry is the other company besides TSMC shipping gate-all-around transistors in volume, and its design enablement engineers are the reason fabless customers can actually tape out on those nodes. The job is less about designing a chip and more about building the PDK, libraries, and rule decks that everyone else designs against.
Day to day that means PDK development, standard cell and I/O library characterization, DFM rule creation, reference flow work, and direct support for customers bringing up a new process. It sits on top of real device physics: CMOS process characterization, SPICE model extraction, and EDA tool calibration against silicon. Knowing how Samsung's GAA MBCFET transistor behaves, and how that shifts design rules away from FinFET, is the detail that gets a résumé read.
The node list runs SF3 (3nm GAA), SF4X (4nm FinFET), SF5A (5nm), and SF8S (8nm), with SF2 (2nm GAA) PDKs in active development. The GAA move at SF3 was not an incremental step. A new transistor architecture forces new PDK methodology and new design rules from the ground up, which is why the enablement teams on SF3 and SF2 work at the front edge of what is commercially available.
These engineers bridge Samsung's fab and its customers, a roster that includes NVIDIA, Qualcomm, IBM, and a long list of AI chip startups. US roles are in San Jose and Austin, with the headquarters teams in Korea; the American offices handle customer-facing enablement for North American fabless accounts. If you are weighing the fab side against a customer role, the TSMC process design engineer jobs make a useful comparison, and we also track foundry design enablement engineer jobs across the other fabs.
Samsung is pushing hard to win advanced-node customers away from TSMC, so these teams are hiring to match. For a sense of how enablement pay compares to design-side roles, the semiconductor salary guide breaks it down by function and level.
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FAQ
What is a Samsung Foundry design enablement engineer
They build and maintain the PDK, standard cell and I/O libraries, and EDA tool configurations that Samsung's fabless customers use to design on Samsung process nodes. The role is the bridge between the fab process and the customer's design team.
What Samsung Foundry process nodes are current design enablement engineers working on
They currently support SF3 (3nm GAAFET), SF4X (4nm FinFET), SF5A (5nm), and SF8S (8nm), and are developing PDKs for the next-generation SF2 (2nm GAAFET) process.
Does Samsung Foundry hire design enablement engineers in the United States
Yes. The San Jose and Austin offices provide customer-facing enablement support to North American fabless customers, and those positions appear regularly on SemiDesignJobs.