How Chips Are Made: From Sand to Silicon

If you work in RTL design, verification, or physical design, your day-to-day sits squarely in one slice of a supply chain that spans five continents, six industrial layers, and decades of compounding specialization. Most engineers understand their own layer in detail and have a rough mental model of the fab downstream. What tends to be underestimated is just how deep the stack goes in both directions - and how a disruption at any single layer can halt everything above it.

This is a technical overview of how a chip actually comes into existence, from the raw materials that precede the wafer to the packaged silicon that eventually lands on a PCB. It is written for engineers who already know what a synthesis run looks like; the goal is to fill in the rest of the picture.

Layer 0: Raw Materials

Before any transistor exists, there is quartz. Metallurgical-grade silicon smelted from quartz runs around 99% purity - completely unusable for semiconductors. Getting to electronics-grade polysilicon requires pushing purity to the parts-per-trillion range through the Siemens process or fluidized-bed reactor methods. That step is performed by a handful of companies: Hemlock Semiconductor in Michigan, Wacker Chemie in Germany, and OCI in South Korea. This is not a long list. If Hemlock has a production incident, it is a US national supply problem.

Beyond polysilicon, the fab ecosystem demands specialty gases (NF3, WF6, HCl), photoresists, copper foil, molding compounds, solvents, and a long tail of chemicals with no commodity substitute. China's 2023-2024 export controls on gallium and germanium - both critical for RF semiconductors and power electronics - made visible what supply chain professionals already knew: the constraint is rarely the ore, it is the refining capacity built around cheap electricity and decades of process know-how.

New refining facilities take years to permit and build. That lead time is one reason upstream disruptions echo so far downstream.

Layer 0.5: Tools and Toolmakers

Chip design is inseparable from the equipment that manufactures it. ASML's EUV scanners are arguably the most complex machines ever built: each one ships with roughly 100,000 components, many sourced from a global network of sole-source suppliers. A single EUV tool costs upward of $150 million and has a lead time exceeding one year. There is no second source.

Tokyo Electron, Lam Research, Applied Materials, and KLA each hold near-monopoly positions on specific fab process steps - deposition, etch, CMP, and metrology respectively. Export restrictions imposed by the US, Netherlands, and Japan on equipment sales to China in 2022-2023 turned these toolmakers into geopolitical instruments. The practical effect: China cannot currently manufacture at leading-edge nodes, not because of design capability gaps, but because the physical equipment is inaccessible.

For engineers working on chips that push process node limits, understanding tool roadmaps matters. What ASML can expose, and when, directly shapes what feature densities are achievable in a given tape-out window.

Layer 1: Chip Design - Where Your Work Lives

The fabless model disaggregated design from manufacturing, and it reshaped the entire industry. Companies like Nvidia, Apple, AMD, and Qualcomm employ large teams of RTL engineers, verification engineers, and physical design engineers who produce the GDSII files that fabs ultimately manufacture - but they never touch a cleanroom.

The design layer depends on EDA software (Synopsys Design Compiler, Cadence Genus for synthesis; Cadence Innovus, Synopsys ICC2 for implementation), licensed IP (Arm cores, PCIe/DDR PHYs, memory compilers), and process design kits tied to a specific foundry node. A modern SoC at 3nm or 5nm might represent 500+ person-years of engineering effort across front-end RTL, verification, DFT insertion, and physical implementation before a single wafer is cut.

Architectural decisions made here cascade downstream. Memory bandwidth choices determine packaging requirements. Power delivery architecture influences substrate design. Die size affects wafer yield and cost. The design layer sets constraints that every other layer has to accommodate.

Layer 2: Wafer Fabrication

This is where GDSII becomes silicon. A leading-edge logic fab is closer to a physics experiment than a factory: wafers move through hundreds of process steps involving photolithography, CVD and ALD deposition, plasma etch, ion implantation, CMP planarization, and copper damascene interconnect. All of it happens in ISO Class 1 cleanrooms, inside tools that cost tens of millions of dollars each, with process control measured in angstroms.

TSMC is the gravitational center of advanced logic. Samsung Foundry sits alongside it at the frontier. Intel Foundry is rebuilding after years of process delays. For mature nodes, GlobalFoundries (US/EU/Singapore), UMC (Taiwan), and SMIC (China) serve automotive, industrial, and analog markets that do not chase leading-edge geometries.

The geographic concentration is stark. The overwhelming majority of leading-edge logic - the chips that power AI accelerators, high-end mobile SoCs, and server CPUs - is manufactured on one island and one peninsula. The April 2024 Hualien earthquake briefly paused TSMC operations, forcing customers across automotive, compute, and industrial sectors to recalculate supply plans. Nothing catastrophic resulted, but the fragility was visible: a few hours of downtime at a single fab ripples through quarters of downstream planning.

CHIPS Act funding is accelerating fab construction in the US and Europe, but standing up a leading-edge fab from greenfield takes a decade. The barrier is not money alone - it is process know-how, an ecosystem of local suppliers, and thousands of process engineers with deep node-specific experience.

Layer 3: Advanced Packaging

A bare die leaving the fab is electrically inaccessible and physically fragile. Packaging transforms it into something that can be mounted, powered, and connected to the rest of a system.

The industry has moved well beyond wire bonding. Modern high-performance packaging includes flip-chip BGA for standard devices, 2.5D interposer configurations (TSMC CoWoS, Intel EMIB) that place multiple chiplets on a silicon or organic substrate, and 3D stacking with through-silicon vias. HBM memory stacked on a logic die via TSVs is now standard for AI accelerators and high-end GPUs.

Outsourced semiconductor assembly and test (OSAT) is dominated by ASE Group, Amkor, JCET, and Powertech. Substrates - the organic interposers that sit between the die and the PCB - come primarily from Ibiden and Shinko in Japan, with Unimicron in Taiwan. When AI demand accelerated in 2023-2024, substrate capacity became a hard constraint independent of wafer supply. The US holds roughly 5% of global OSAT volume within its borders, a gap that CHIPS Act advanced packaging initiatives are attempting to address.

Advanced packaging is increasingly a performance differentiator, not just a commodity step. Decisions made in chip design around I/O placement, bump pitch, and die-to-die interface standards (UCIe, BoW) have direct implications for which packaging configurations are achievable.

Layer 4: Boards, Assembly, and Distribution

Packaged dies move into a broader electronics supply chain involving PCB fabrication, PCBA assembly, and EMS firms. PCB fabrication is heavily concentrated in China, with Taiwan, South Korea, and Vietnam handling significant volume. The 2021 Vietnam COVID shutdowns illustrated a structural vulnerability that applied not to advanced chips but to the $3 FR4 boards without which $500 systems cannot ship.

EMS firms - Foxconn, Pegatron, Jabil, Flex, Celestica - operate at staggering scale. Foxconn's Zhengzhou facility, optimized for iPhone assembly, employed hundreds of thousands of workers on a single campus. When it faced extended disruptions in late 2022, the effects were immediately visible on retail shelves. That direct visibility to consumers is unusual; most supply chain failures stay invisible until a lead time extends or an allocation notice lands.

Component distributors (Arrow, Avnet, Digi-Key, Mouser) sit across all of this, providing inventory buffering, lifecycle management, and demand smoothing that OEMs cannot replicate internally. During the 2020-2022 automotive chip crisis, the bullwhip effect played out in full: automakers cancelled orders early in the pandemic, then scrambled to reorder six months later into a market where consumer electronics had absorbed all available capacity. A single missing microcontroller - a $1 part - halted $40,000 vehicles.

Why This Matters for Engineers

The semiconductor supply chain is not just background context for the work you do in design. It shapes what is buildable, what process nodes are accessible, what packaging configurations are economically viable, and which architectural tradeoffs make sense given manufacturing constraints.

Understanding where materials come from, why certain equipment is geopolitically contested, and how packaging capacity can be as constraining as wafer starts makes you a more effective architect, not just a better implementer. It also helps decode why tape-out schedules slip, why certain IP vendors are more reliable than others, and why the foundry roadmaps you depend on are shaped by forces well upstream of any design review.

If you are navigating where to take your career in this industry, the semiconductor design career path guide covers how discipline choice, company type, and node focus intersect with the broader market.

The jobs that drive this stack - from EDA tool development to physical design to packaging architecture - are listed at semidesignjobs.com.