Verification Engineer Intern

Role Overview

As a Verification Engineer Intern, you will work with a team of engineers to support the development of cutting-edge VLSI design projects at Ambarella. This internship is ideal for students nearing the completion of their master's degree who have a keen interest in programming, computer architecture, and VLSI design.

Experience Level

This position is suited for early-career professionals, particularly those still pursuing their education and seeking practical experience in a professional engineering environment.

Key Responsibilities

• Develop test benches or components, writing and debugging tests and RTL logic.
• Create Random Test Generators to intelligently produce tests.
• Implement coverage monitors, checkers, and assertions while gathering performance statistics.
• Design tools, scripts, and utilities for stimulus creation and simulation result analysis.

Essential Requirements

The internship requires familiarity with programming and scripting languages such as Verilog, System Verilog, UVM, C, C++, Perl, Python, or assembly code. Interns should be capable of quickly acquiring new skills and reliably completing assigned tasks.

Education Requirements

This role requires students who are in their final stages of pursuing a master's degree in a relevant field such as Electrical Engineering, Computer Science, or a related discipline.