Verification Engineer

Role Summary

The Verification Engineer will be responsible for creating detailed verification environments and ensuring the accuracy of product design through testing. This role involves working closely with design teams to develop test plans, implement test case scenarios, and debug and troubleshoot design issues.

Experience Level

This position is categorized as Level - Mid-Career.

Responsibilities

• Develop and execute verification plans and test cases.
• Collaborate with cross-functional teams to identify and mitigate potential issues.
• Analyze and resolve design issues through detailed debugging.
• Document and report test results and findings effectively.

Requirements

• Bachelor's degree in Electrical Engineering or a related field.
• Minimum 3 years of experience in verification environments, specifically in ASIC or FPGA domain.
• Strong coding skills in SystemVerilog or similar languages.
• Experience with UVM methodology is highly preferred.
• Ability to work independently and as part of a team in a fast-paced environment.

Education Requirements

Minimum of a Bachelor's degree in Electrical Engineering or a closely related field.