UFS IP Verification Engineer

Role Overview

The UFS IP Verification Engineer plays a crucial role in the AMD IO IP verification team, focusing on the verification of host controller IP for next-generation high-speed IO implementations.

Role Summary

The candidate will engage in IP verification tasks, applying advanced verification techniques to enhance pre-silicon quality and expedite time to market for ASIC/SOC projects.

Experience Level

Preferred candidates will hold either a Master’s or Bachelor’s degree in Electrical Engineering, Computer Science, or a related field, along with substantial experience in digital ASIC/SOC design verification.

Responsibilities

The responsibilities include:

• Engaging with team members to apply functional verification techniques.
• Leading technical discussions across multiple product lines.
• Coaching and mentoring junior engineers.
• Promoting best practices in design verification.
• Ensuring high-quality execution in project timelines and deliverables.

Requirements

Candidates must possess:

• A deep understanding of ASIC/SOC design flows.
• Knowledge of design verification methodologies like UVM and FPV.
• Experience in simulation model creation and testbench development.
• Strong skills in RTL coding with Verilog.
• Robust C/C++ development experience.
• Familiarity with scripting languages such as Perl and C shell.

Education Requirements

Master’s or Bachelor’s degree in Electrical Engineering, Computer Science, or a closely related field is required.