System DV Engineer

Role Summary

The System DV Engineer will work collaboratively with designers and firmware teams to establish an innovative test environment that enhances System Design Verification efficiency and quality. This role involves integrating hardware, firmware, and system workload to improve development flow using advanced methodologies.

Experience Level

Mid-level; minimum of 5 years of experience in SoC Design Verification.

Responsibilities

The responsibilities include:

• Creating a test environment to enhance System Design Verification.
• Working with cross-functional teams and integrating system-level components.
• Identifying opportunities for development flow improvement using AI and ML.
• Building test plans and ensuring coverage closure.
• Achieving DV quality signoff.

Requirements

Must-have qualifications include:

• Expertise with ASIC simulation tools and verification methods.
• 5+ years of SoC Design Verification experience using UVM System Verilog methodology.
• Strong scripting skills, preferably in System C or C++.
• Experience with SoC and CPU emulation verification.
• Good communication skills in English and Mandarin.

Nice-to-have qualifications include:

• Experience in creating Design Verification Testbenches in System C.
• Experience with DRAM or NAND protocols.
• Knowledge of AI/ML applications.

Education Requirements

B.S. or higher in Electrical Engineering or Computer Science related fields.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.