Synthesis Engineer

Role Overview

The Synthesis Engineer will play a critical role in developing and validating timing constraints for complex SoC designs at Celestial AI. This position requires expertise in timing constraints development, synthesis, and front-end implementation methodologies for both SOC and block levels.

Experience Level

The ideal candidate should possess a minimum of 5 years of industry experience focused on ASIC implementation, static timing analysis (STA), and synthesis.

Key Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate across teams (Architecture, RTL, DFT, Analog) to analyze design requirements and develop consolidated timing modes for various implementation flows.
• Own and contribute to tasks related to Synthesis, UPF development, and Logical Equivalence Checks (LEC).
• Analyze trade-offs between power, performance, and area to optimize chip implementation.
• Perform static timing analysis using industry-standard tools such as Tempus or Primetime.
• Define and implement signoff methodologies, including process corners and uncertainties.
• Automate flows and processes using scripting languages like Tcl or Python.
• Create QoR dashboards and ensure compliance with timing signoff criteria.

Qualifications

• Bachelor's degree in electrical or computer engineering; an advanced degree is preferred.
• 5 years of experience in ASIC synthesis, timing constraints, and static timing analysis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Hands-on experience with synthesis tools and STA methodologies.
• Familiarity with advanced technology nodes (TSMC N4/N5) and experience in high-complexity silicon is a plus.
• Excellent problem-solving, attention to detail, and communication skills.

Education Requirements

Bachelor's degree in electrical or computer engineering, with an advanced degree preferred.