Staff/Sr. Staff RTL Design Engineer

Role Summary

This position involves the development and validation of advanced embedded memory test and SLM architectures. The ideal candidate will have expertise in digital design and verification, including a thorough understanding of RTL logic design, functional verification, and automation techniques.

Experience Level

3-5 years of professional experience in ASIC design and verification, with practical knowledge of methodologies and tools in digital design.

Responsibilities

• Develop and model RTL logic in Verilog for embedded memory and SLM IP blocks.
• Perform digital design validation and functional verification at both block and SoC levels.
• Execute logic synthesis and static timing analysis, generating fault coverage reports.
• Apply DFT expertise for memory and logic testing.
• Identify and troubleshoot timing and DFT functional issues.
• Scripting in Tcl to automate design and verification workflows.
• Define architecture and embedded software functions for advanced tests.
• Develop and maintain technical documentation and test collateral.
• Collaborate with R&D and marketing to drive enhancements and product features.
• Deliver product training and manage customer support cases.

Requirements

• Bachelor's degree in Electrical Engineering or related field.
• Proficiency in RTL simulation using tools and languages such as SystemVerilog and UVM.
• Deep understanding of established protocols including IEEE1500 and AMBA.
• Hands-on experience in simulation and emulation environments.
• Programming skills in Verilog, C/C++, Python, and scripting languages.
• Familiarity with EDA tools such as VCS, Verdi, and diagnostics tools.
• Ability to communicate effectively across disciplines and with external partners.
• Analytical and problem-solving skills, focused on quality and detail.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required.