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Staff R&D Software Engineer - VC Platform

Synopsys
Full-time
On-site
Noida, India
Level - Mid-Career

Role Overview

As a Staff R&D Software Engineer at Synopsys, you will partake in developing core technologies that enhance the EDA tool ecosystem, particularly focusing on the VC Platform. Your role involves deep engagement in hands-on software development, requiring a strong application of your skills across both hardware and software domains. You will work closely with cross-functional teams to innovate and deliver advanced solutions that simplify and expedite chip design processes.

Position Summary

The position is designed for an engineer with 4 to 10 years of software development experience, specializing in C++ and EDA methodologies. You are expected to possess a solid foundation in electronic design automation and hands-on experience with hardware description languages. The role emphasizes the design and troubleshooting of the VC-Static engine, ensuring that the solutions are robust and scalable, with a focus on quality and performance.

Experience Level

4 to 10 years of professional experience in software development, particularly in C++ programming, with a strong emphasis on data structures, algorithms, and object-oriented design principles.

Responsibilities

  • Designing and troubleshooting the core VC-Static engine and ensuring system robustness.
  • Architecting object models for hardware description languages to support EDA tool functionalities.
  • Collaborating with global teams for product integration and feature delivery.
  • Creating new algorithms focused on enhancing electronic design automation tools.
  • Maintaining high-quality production code while evolving HDL parsers on Unix/Linux platforms.
  • Employing C++ and algorithm analysis to address performance and scalability challenges.
  • Using Tcl and Perl for workflow automation and to enhance tool usability.

Requirements

Applicants should have a strong C++ programming background, and knowledge of data structures, algorithm analysis, and ASIC design flow. Experience with Verilog, SystemVerilog, and VHDL is essential, along with hands-on experience in scripting languages in Unix/Linux environments. Familiarity with HDL parser development and a knowledge of GenAI concepts will be viewed favorably.

Education Requirements

A degree in Computer Science, Electrical Engineering, or a related field is preferred, along with relevant software development experience.