Staff Memory PHY RTL Design Engineer

Role Summary

The Memory PHY team is seeking an experienced Design Engineer to focus on RTL and Firmware development for high-speed LPDDR and DDR IPs. The role involves defining, designing, and developing top-tier Memory PHYs and interface IP, alongside creating new IO designs and improving methodologies.

Experience Level

This position is suited for experienced professionals who possess a strong foundation in digital design and have demonstrated success in collaborating with multifaceted engineering teams.

Responsibilities

The primary tasks include:

• RTL design for memory I/O.
• Development of PHY Digital Architecture from initial coding to physical implementation.
• Link layer design, implementation, and verification.
• Engagement in both Analog and Digital co-design.
• Conducting timing synthesis and driving physical implementation.
• Collaborating with architects and engineers to comprehend new features.
• Estimating timelines for feature tests and necessary changes.
• Constructing unit tests.
• Troubleshooting design failures and correcting test issues.

Requirements

The ideal candidate should have:

• Experience in digital design engineering.
• Proficiency in Verilog, System Verilog, and scripting languages like Python, Perl, or TCL.
• Knowledge of clocking architectures and CDC methodology.
• Experience with synthesis and timing closure.
• Background in SERDES, DDR, or Memory Controller design.
• Ability to debug firmware and RTL code.
• Strong grasp of computer organization and architecture.
• Exposure to mixed signal RTL and low-power design is advantageous.
• Leadership or mentorship capabilities are preferred.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.