Staff FPGA Design Engineer

Role Overview

The Staff FPGA Design Engineer role involves planning, building, and executing the verification processes for new and existing features of AMD’s graphics processor IP. The primary goal is to ensure that the final design is free of bugs, thereby enhancing the functionality of the product.

Job Summary

As part of a small team, the selected candidate will work closely with architects and engineers across various locations to facilitate seamless collaboration on feature verification. Strong communication skills and a passion for processor architecture and digital design are vital in this role.

Experience Level

This position is aimed at candidates with mid-level to senior experience in FPGA design and verification.

Key Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers regarding new feature verification.
• Develop comprehensive test plan documentation considering interactions among features, hardware, firmware, and software.
• Estimate timelines for feature test creation and adjustments to the testing environment.
• Construct both directed and random verification tests.
• Troubleshoot test failures to determine root causes, collaborating with engineers to resolve defects.
• Review functional and code coverage metrics; modify tests as necessary to meet coverage requirements.

Job Requirements

Applicants should have proficiency in ASIC verification, strong debugging skills for firmware and RTL code, and the ability to work in both Linux and Windows environments. Experience with Verilog, System Verilog, C, and C++ is essential, alongside knowledge of graphics pipelines and developing verification frameworks using UVM.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required for this position.