Staff Engineer - SerDes Timing Analysis Engineer

Role Overview

As a Staff Engineer specializing in SerDes Timing Analysis at Synopsys, you will play a pivotal role in designing and analyzing integrated circuit systems specifically focused on high-speed communication interfaces. Your expertise will contribute significantly to the development of innovative products within the analog design team.

Experience Level

This position is suitable for mid-career professionals with substantial experience in analog or mixed-signal design. Candidates should have a track record of effective project involvement in the field.

Key Duties

• Conduct timing analysis on SerDes designs to ensure functionality and performance parameters are met.
• Collaborate with cross-functional teams to integrate design inputs and validate outputs through simulation and testing.
• Identify and resolve design issues, providing innovative solutions to complex engineering challenges.
• Create detailed documentation and reports on design analysis and testing outcomes.
• Mentor junior engineers and assist them in their professional development.

Qualifications

Candidates should possess strong analytical skills and hands-on experience in analog circuit design, particularly regarding high-speed communications. Proficiency in relevant tools and methodologies for timing analysis is essential.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering or a related field is required.