Staff Digital Design Engineer - DSP

Role Overview

This position is for an experienced engineer specializing in digital signal processing (DSP) algorithms applied to high-speed SerDes systems (Serializer/Deserializer). The role involves evaluating, designing, and optimizing DSP algorithms and circuits aimed at achieving over 200 Gbps data rates, focusing on improving power efficiency and overall performance.

Professional Level

This role is ideally suited for professionals with significant experience in digital design engineering, particularly in DSP and SerDes technologies. Candidates should be adept at collaborating within multi-disciplinary teams in a fast-paced environment.

Core Responsibilities

• Collaborate with architects, hardware, and verification engineers to define new DSP features for next-generation SerDes transceivers focused on low power consumption.
• Implement DSP algorithms for tasks such as equalization, filtering, and sequence detection.
• Engage in RTL development and utilize front-end ASIC tools to maintain code quality.
• Prepare comprehensive documentation of DSP algorithm behavior and its integration with SerDes hardware and software.

Qualifications Needed

Ideal candidates will have a demonstrated background in DSP algorithm development, particularly within the realm of SerDes applications, wireless communications, or high-speed serial interfaces like Ethernet and PCIe. Familiarity with various equalization techniques and a strong foundation in RTL design using SystemVerilog is crucial. An understanding of digital design optimization for low-power applications is also expected.

Education Requirements

A Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field is required for this position.