Role Summary
This position is focused on digital signal processing (DSP) algorithms and their implementation in high-speed serializer/deserializer (SerDes) systems. The role involves optimizing R&D efforts to enhance AMD's connectivity solutions.
Experience Level
Mid-Career experience is preferred, particularly in DSP and digital design for high-speed communication systems.
Responsibilities
The primary responsibilities include:
- Collaborating with architects and engineers to refine DSP features for SerDes transceivers.
- Implementing DSP algorithms for equalization, filtering, and sequence detection.
- Conducting RTL development utilizing ASIC front-end tools to ensure code quality.
- Creating detailed documentation for DSP algorithms and their interaction with hardware and software components.
Requirements
Applicants should meet the following requirements:
- Proven experience in DSP algorithm development for SerDes or similar interfaces (e.g., Ethernet, PCIe).
- Knowledge of equalization techniques (FFE, CTLE, DFE, MLSE).
- Strong digital design experience, including clock domain crossing and RTL using SystemVerilog.
- Understanding of power optimization techniques in digital design.
- Familiarity with simulation and modeling of DSP blocks.
Education Requirements
A degree in Electrical Engineering or related field is typically expected for this role.