Staff DFT Engineer

Role Summary

The Staff DFT Engineer is responsible for developing and verifying Design-for-Test (DFT) methodologies for complex silicon designs, ensuring high defect coverage and effective testing in manufacturing environments.

Experience Level

This position requires candidates to have significant experience, with at least 3-5 years in related professional roles for a Bachelor’s degree or 2-3 years with a Master’s degree in Computer or Electrical Engineering. A PhD may also be acceptable based on the specific experience.

Responsibilities

• Develop an understanding of block-level and chip-top design-for-test (DFT) and automated test pattern generation (ATPG) flows.
• Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test.
• Analyze test results and implement improvements to test coverage.
• Collaborate with the global DFT team for design flow improvements.
• Support manufacturing test hardware bring-up and pattern debugging.

Requirements

Qualified candidates must have digital logic design skills, familiarity with Verilog, and hands-on experience with various testing methodologies. Proficiency in EDA DFT tools like Siemens EDA Tessent, Cadence Modus, or Synopsys TestMAX, as well as programming skills in TCL, Python, Perl, or csh/bash in a Unix environment, are also necessary. Good problem-solving skills and communication abilities are essential.

Education Requirements

Bachelor of Science degree in Computer or Electrical Engineering, Master of Science degree in the same fields, or a PhD in Computer or Electrical Engineering is required.