Staff Design Verification Engineer

Role Overview

The Staff Design Verification Engineer at Synopsys will play an integral role in our engineering team, focusing on ASIC Digital Design. This position is based in Noida, Uttar Pradesh, India.

Experience Level

This position is classified as a Mid-Career role, looking for candidates with significant experience in design verification.

Key Responsibilities

As a Staff Design Verification Engineer, your responsibilities will include:

• Developing and implementing verification plans.
• Creating and maintaining test benches using industry-standard languages and methodologies.
• Collaborating with design teams to ensure comprehensive coverage.
• Performing thorough debugging and root cause analysis.
• Documenting verification results and providing feedback for design improvements.

Qualifications and Skills

Candidates should possess the following qualifications:

• Strong knowledge of digital design and verification methodologies.
• Proficiency in programming languages such as SystemVerilog or VHDL.
• Experience with simulation tools and environments.
• Excellent problem-solving and analytical skills.
• Ability to work collaboratively in a fast-paced environment.

Education Requirements

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required. Advanced degrees are preferred but not mandatory.