Staff Application Engineer

Role Summary

The Staff Application Engineer will develop and execute formal verification strategies for complex hardware designs, ensuring their correctness and reliability. This engineer will work closely with design and validation teams to perform various new product verification tasks.

Experience Level

This position requires at least 3 years of relevant experience in the engineering field.

Responsibilities

The key responsibilities of this role include:

• Developing and implementing formal verification plans for RTL designs across various customer projects.
• Debugging formal failures and collaborating with design teams to resolve issues effectively.
• Identifying critical bugs in the Formal Verification and ECO flow and reporting them to research and development teams.

Requirements

The essential requirements to qualify for this role are as follows:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• A minimum of 3 years' experience in the field.
• Strong understanding of digital design concepts, UPF methodology, and formal equivalence flows.
• Hands-on experience with formal verification methodologies, ECO execution, and static low power checks.
• Experience with RTL languages such as Verilog or System Verilog.
• Strong debugging and problem-solving skills.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field is required for this position.