Sr. Staff RTL Design Engineer - PCIe

Job Title

Sr. Staff RTL Design Engineer - PCIe

Role Summary

The Sr. Staff RTL Design Engineer will own PCIe/CXL subsystem micro-architecture, RTL implementation, and integration for data-center SoC products. The role works within the Compute & Storage BU and requires cross-functional collaboration with architecture, verification, physical design, DFT, firmware, and validation teams.

Primary mission: deliver robust, PD‑friendly, and DFT‑ready RTL for PCIe/CXL subsystems, support silicon bring‑up and post‑silicon debug, and provide technical leadership and mentoring within the PCIe/CXL domain.

Experience Level

Senior — typically 8+ years of relevant RTL design experience (as stated in the posting).

Responsibilities

Key responsibilities include:

• Define and drive PCIe/CXL subsystem micro-architecture and RTL implementation.
• Translate architecture requirements into robust RTL designs in collaboration with architecture teams.
• Coordinate with Design Verification teams on test plans, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure PD‑friendly and DFT‑ready RTL.
• Support silicon bring‑up and post‑silicon debug with firmware and validation teams.
• Improve design quality, enforce coding best practices, and promote reuse across projects.
• Participate in design and milestone reviews and cross‑functional technical discussions.
• Mentor junior designers and provide technical leadership in the PCIe/CXL domain.

Requirements

Technical skills and experience required or strongly preferred.

Must-have:

• End-to-end PCIe/CXL subsystem RTL design experience, including execution and sign‑off.
• Proven delivery of complex PCIe/CXL IP or subsystems from architecture to RTL closure.
• Hands‑on SystemVerilog / Verilog RTL development.
• Deep knowledge of PCIe protocol architecture (link, transaction, PHY interaction).
• Understanding of CXL.io, CXL.cache, and CXL.mem architectures.
• Experience with ARM‑based SoC integration and AMBA protocols (AXI‑4, CHI, ACE).
• Design experience for high‑performance, low‑latency data paths; ordering, coherency, and error handling.
• Solid grasp of clocking, resets, CDC/RDC, low‑power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC, synthesis, and design sign‑off flows.
• Proficient debugging of functional and performance issues at subsystem and SoC levels.
• Experience with EDA tool flows (Synopsys, Cadence, Mentor/Siemens).
• Proficient in scripting (Tcl, Perl, Python) and version control systems (GIT, SVN).

Nice-to-have:

• Experience specifically with silicon bring‑up and post‑silicon validation workflows.
• Previous leadership or mentoring roles within large RTL teams.

Education Requirements

Master's or Bachelor's degree in Electronics / Electrical Engineering (the posting specifies "Master’s/Bachelor’s degree in Electronics/electrical Engineering") and 8+ years of relevant RTL design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.