Sr. Staff Engineer - ASIC Digital Design for SERDES IP

Role Summary

As a Senior Staff Engineer specializing in ASIC Digital Design at Synopsys, you will be instrumental in designing and developing high-speed SERDES PHY IP for next-generation silicon chips. This role requires a strong technical background in micro-architecture and RTL coding, and a passion for collaborating with cross-functional teams to deliver high-quality designs.

Experience Level

This position requires an experience level of 8 to 12 years in ASIC digital design, with a focus on RTL coding and micro-architecture in a professional setting.

Responsibilities

• Analyze complex IP specifications and create robust micro-architectures.
• Develop high-quality RTL code in Verilog/SystemVerilog for SERDES PHY IP blocks.
• Collaborate with verification and architecture teams to resolve design issues.
• Support verification teams by debugging and addressing functional issues.
• Utilize ASIC development tools and manage waivers as necessary.
• Mentor junior engineers and share best practices.
• Participate in design reviews and contribute to improving design methodologies.

Requirements

Applicants must possess a Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field. Experience with Verilog/SystemVerilog and familiarity with VHDL is essential, along with proficiency in high-speed interface protocols such as PCIe and Ethernet. Candidates should also have hands-on experience using ASIC development tools, a firm understanding of the RTL to GDSII process, and scripting skills in Shell or Perl for automation.

Education Requirements

Degree required: Bachelor’s or Master’s in Electrical/Electronics Engineering or a related field.