Sr. Silicon Verification Engineer

Role Summary

As a Senior Silicon Verification Engineer, you will work with graphics architects and designers to verify AMD graphics logic and drive convergence.

Experience Level

Minimum 7 years relevant experience preferred.

Responsibilities

You will be responsible for the following:

• Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal methods to verify design.
• Ensure verification quality metrics like pass rates, code coverage, and functional coverage.
• Drive formal verification for blocks and write formal properties and assertions to verify designs.
• Coordinate with RTL engineers to implement logic design for better clock gating and verify various aspects of the design.
• Adopt AI tools to improve efficiency and quality.

Requirements

The following qualifications are expected:

• Hands-on experience with UVM, test-bench, coverage, etc.
• Project-level experience with design concepts and verifications.
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics.
• Good understanding of computer architecture.

Education Requirements

Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering along with related ASIC verification experience is preferred.