Sr. RTL Design Engineer with DDR protocols exp

Role Summary

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD’s DDR IPs.

Experience Level

5+ years of relevant experience.

Responsibilities

Key responsibilities include:

• Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards.
• Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions.
• Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms.
• Work closely with silicon design, verification, and system engineering teams to ensure seamless integration and interoperability across the full memory subsystem.
• Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior.
• Stay updated with emerging DDR technologies and propose innovative solutions to improve calibration robustness and reduce boot time.

Requirements

The following qualifications are preferred:

• Educational background of B.E/M.E/M.Tech or B.S/M.S in Electrical Engineering/Computer Engineering.
• Digital design experience with RTL design in Verilog/SystemVerilog.
• Knowledge of system-level architecture including buses like AXI/AHB.
• Experience with circuit timing/STA, and familiarity with version control systems such as Perforce, ICManage, or Git.
• Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards.
• Strong verbal and written communication skills.

Education Requirements

Bachelors or Masters degree in Electrical Engineering or Computer Engineering with 5+ years of experience.