Sr. Principal Verification Engineer

Role Summary

The Sr. Principal Verification Engineer will take charge of verification methodologies, particularly focusing on performance analysis and architectural validation tasks. The role requires working closely with cross-functional teams to ensure the integrity and robustness of design implementations.

Experience Level

This position is targeted towards mid-career professionals with extensive experience in verification processes within complex design environments.

Responsibilities

• Lead verification planning and execution for high-performance semiconductor designs.
• Develop and maintain verification environments and testbenches.
• Collaborate with design engineers to identify verification needs and metrics.
• Utilize SystemVerilog and UVM methodologies for effective verification.
• Drive root cause analysis for any reported issues.
• Evaluate and implement improvements in verification methodologies.

Requirements

• Minimum of 5 years of experience in verification engineering within the semiconductor industry.
• Strong understanding of digital design concepts, verification tools, and methodologies.
• Experience with SystemVerilog and UVM is highly desirable.
• Excellent problem-solving and communication skills.
• Ability to work independently and in a team environment.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field is required. A Master's degree is preferred.