Sr. Principal Digital IC Designer

Job Title

Sr. Principal Digital IC Designer

Role Summary

The Senior Principal Digital IC Designer will join Central Engineering to architect, implement, verify and optimize high-performance switch and interconnect IP (UALink-related designs) used across multiple product lines. This is an individual contributor/technical leadership role working with a small experienced digital design team, system architects, verification and implementation teams, and silicon bring-up labs.

The role involves end-to-end ownership from micro-architecture and RTL coding to verification, timing closure and maintenance of reusable IP blocks. The position may require eligibility for access to export-controlled technology.

Experience Level

Senior-level (senior/principal engineer).

Responsibilities

The core responsibilities focus on delivering production-quality digital IP for high-speed interconnects and switch fabrics across the full design lifecycle.

• Define and document micro-architecture and register specifications for complex switch/interconnect blocks.
• Design, implement and verify SystemVerilog RTL for control and data-path logic.
• Participate in full design lifecycle: RTL coding, test-plan reviews, verification coordination, and silicon block bring-up.
• Work with system and chip architects to meet system-level requirements and performance targets.
• Collaborate across RTL design, synthesis, STA and implementation flows to achieve timing closure and QoR goals.
• Produce reusable, modular RTL components suitable for large multi-block systems.
• Conduct design reviews with cross-functional teams and drive improvements in design and verification methodologies.
• Mentor and supervise other digital design engineers; provide technical leadership on complex blocks.

Requirements

Must-have technical skills and experience; listed concisely below. Education degree requirements are summarized in the Education Requirements section.

• Proven experience defining micro-architecture for high-speed interconnects, switch fabrics, or scalable on-chip/off-chip communication systems.
• Strong SystemVerilog RTL design skills for complex control and data-path logic.
• Experience creating scalable, modular, reusable RTL for large multi-block designs.
• Solid understanding of switch design, packet/transaction-based data movement, and performance/latency trade-offs.
• Familiarity with synthesis and static timing analysis (STA) and timing-closure practices for high-performance designs.
• Experience collaborating across RTL design, synthesis and implementation to meet timing, performance, and QoR targets.
• Experience with embedded micro-controller integration and hardware–software interaction in SoC or networking designs.
• Ability to manage multiple projects in a fast-paced technical environment and demonstrate technical ownership and leadership.
• Experience coordinating silicon bring-up and block-level lab testing.

Nice-to-have:

• Experience with I2C, SPI, SMBus or similar control/configuration interfaces.
• Familiarity with SystemVerilog verification techniques (assertions, self-checking testbenches, constrained stimulus).
• Exposure to low-power design techniques, power-aware RTL design, or clocking strategies.

Education Requirements

Degree and experience guidelines stated in the posting: Bachelor's degree in Computer Science, Electrical Engineering or a related field with 15+ years of relevant industry experience; or Master's degree with ~10–12 years of experience; or PhD with ~8–10 years of experience. Fields referenced: Computer Science, Electrical Engineering, or related technical fields. No certifications were specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.