Sr. Design Verification Engineer (Silicon Engineering)

Role Summary

We are seeking a motivated, proactive, and intellectually curious engineer to develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures. This position involves working alongside cross-disciplinary teams to expand the performance and capabilities of the Starlink network.

Experience Level

5+ years of experience in design verification and test bench development.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Execute test plans, run regressions, and achieve code and functional coverage closure.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
• Proactively verify complex digital designs as a hands-on self-starter.

Requirements

Education Requirements

Bachelor’s degree in electrical engineering or computer engineering.

Preferred Skills and Experience

• Advanced degree in electrical engineering or computer engineering.
• Experience with verification methodologies such as UVM/OVM/VMM.
• Strong object-oriented programming knowledge.
• Strong problem-solving and coding skills.
• Experience in constrained random verification.
• Expertise in developing test plans, implementing coverage models, and analyzing results.
• Familiarity with scripting languages, e.g., Python for automation.
• RTL design, chip bring-up, and post-silicon validation experience.
• Able to work in a dynamic environment with changing needs and requirements.

Additional Requirements

Must be willing to work extended hours and weekends as needed.