Sr Design Verification Engineer

Role Summary

This position offers an opportunity to be part of Lattice’s Silicon Engineering team, contributing to verifying complex FPGAs. You will craft reusable UVM test benches, implement coverage-driven test cases, and improve quality for tape-out readiness, collaborating across product development teams.

Experience Level

Level - Mid-Career

Responsibilities

• Contribute to design verification of cutting-edge FPGAs.
• Integrate sophisticated design and verification environments.
• Develop effective verification plans and test benches.
• Collaborate with various teams to enhance FPGA systems.
• Address complex design verification challenges.

Requirements

• BS/MS in Electrical Engineering, Computer Science, or equivalent.
• Minimum 6+ years of experience in design verification, with 2+ years leading complex IP verification.
• Expertise in System Verilog and UVM methodology.
• Experience with verifying IPs like PCIExpress, Ethernet, or USB.
• Hands-on experience in low power design and firmware verification.
• Strong communication and problem-solving skills.

Education Requirements

BS/MS in Electrical Engineering, Computer Science, Computer Systems Engineering, or a related field.