Sr. Design Verification (DFT-FV)

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

Experience Level

Mid-Career

Responsibilities

• Collaborate with architect and hardware engineers, to understand the new features to be verified.
• Create block-/chip-level Design Verification (DV) test plan.
• Create methodology-based (UVM) verification testbenches and components from scratch.
• Develop test cases, behavioral functional models and testbench.
• Understand Design-for-Test (DFT) and Design-for-Debug (DFD) architecture.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues.
• Quality deliverables through regressions.
• Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness.

Requirements

• Proficient in IP level ASIC verification.
• Proficient in debugging firmware and RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.

Education Requirements

Bachelors or Masters degree in computer engineering or Electrical Engineering.