Sr. ASIC Design Engineer

Role Summary

We are looking for a Sr. ASIC Design Engineer to join a team focused on developing advanced FPGAs and ASICs for SpaceX's satellite communications system, Starlink. The selected candidate will contribute to the design and verification of next-generation chips that enhance global connectivity.

Experience Level

This position requires a mid-career professional with a minimum of 5 years of relevant experience in RTL implementation.

Responsibilities

The responsibilities for this role include:

• Evaluating architectural trade-offs for features and performance requirements.
• Defining micro-architecture and implementing RTL in Verilog/System Verilog.
• Collaborating with the verification team to ensure comprehensive design verification.
• Providing timing constraints and supporting the physical implementation team.
• Participating in silicon bring-up and validation processes.

Requirements

Candidates must possess the following qualifications:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.
• Ability to solve complex problems, including clock domain crossings and power optimization.
• Experience with ASIC/SoC system integration and multicore CPU subsystems.
• Familiarity with standard bus protocols and embedded processors.
• Knowledge of high-speed and low-power design techniques.
• Scripting skills (Python, TCL, etc.) and experience with EDA tools.
• A team-oriented mindset with strong adaptability to changing environments.
• Willingness to work extended hours and weekends as needed.

Education Requirements

Applicant must have a Bachelor's degree in electrical engineering, computer engineering, or computer science.