Soft IP Design Engineer

Role Summary

Design Engineer role focused on developing Connectivity IP portfolios for Lattice FPGA, involving high-speed RTL design translating specifications into performance-optimized designs.

Experience Level

Minimum of 3 years of FPGA IP design experience, with a strong background in electronics or computer engineering.

Responsibilities

• Collaborate with architects to design high-speed RTL solutions.
• Ensure optimal performance, power, and logic utilization.
• Work in a dynamic environment, adapting to changing specifications.

Requirements

• BS/MS/PhD in Electronics or Computer Engineering.
• Experience in high speed SERDES protocols (Ethernet, CPRI, JESD204B/C) or Parallel IOs (DDR, SPI, I2C, I3C).
• Hands-on experience in FPGA RTL design, logic verification, debug, and timing closure.
• Programming skills in C/C++, Perl, TCL, or Python.
• Experience in hardware validation, interoperability testing, soft IP packaging, and testbench development is a plus.

Education Requirements

BS/MS/PhD in Electronics or Computer Engineering is required.