SOC RTL Integration Engineer

Role Summary

The SOC RTL Integration Engineer will be responsible for building full-chip RTL connectivity models and integrating RTL components from various design teams. The role involves verifying that full chip models match architectural intent and developing custom tools and methodologies to enhance development efficiency and quality.

Experience Level

Level - Mid-Career

Responsibilities

• Develop Full Chip SOC RTL
• Develop timing constraints and validate them
• Write Full Chip Design Specification document
• Work with IP development team to integrate IPs
• Collaborate with architecture, SW and verification teams to ensure Full Chip SOC RTL quality
• Run lint and CDC tools and generate timing constraints

Requirements

Applicants should have experience in SOC RTL or Front-End integration, with strong expertise in timing constraints development and validation.

• Strong experience using FPGAs and understanding FPGA architectures in a semiconductor environment
• Proven expertise with timing tools such as PrimeTime and Fishtail
• Familiar with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.)
• Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog
• Good waveform debug skills using industry standard design tools like VCS, NC Sim, or Verdi
• Familiarity with Unix/Linux environment and scripting languages such as Perl or Python
• Some experience with Revision Control tools – CVS, Subversion, or Perforce
• Strong presentation skills

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.