SOC DFT Design Engineer

Company Overview

Advanced Micro Devices (AMD) is a technology company dedicated to building high-performance computing products, including microprocessors and graphics solutions for various applications.

Role Summary

The SOC DFT Design Engineer will work within a centralized ASIC design group at AMD. This position focuses on developing and implementing Design-for-Test (DFT) and Design-for-Debug (DFD) features for next-generation products.

Experience Level

Minimum 8 years of experience in DFT or related domains is required, with prior leadership of DFT efforts for large processor or SOC designs preferred.

Responsibilities

• Develop RTL for ASIC design-for-test (DFT) features as per specifications.
• Integration, insertion, synthesis, and verification of DFT RTL designs.
• Work with multi-functional teams to manage schedules.
• Create CAD software and scripts to support DFT implementations.
• Perform scan insertion, ATPG verification and pattern generation.
• Support production engineering teams during first silicon bring-up and debug activities.

Requirements

• Expertise in DFT techniques including JTAG/IEEE standards and ATPG methodologies.
• Proficient in Verilog simulation and debugging tools for both RTL and gate level simulations.
• Knowledge of scripting languages (TCL, c-shell, Perl) and UNIX/Linux environments.
• Familiar with RTL quality checks and EDA tools such as synthesis and static timing analysis.
• Strong problem-solving capabilities and team collaboration skills.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.