SOC Design Verification Engineer (Silicon Engineering)

Role Summary

We are seeking a motivated, proactive, and intellectually curious engineer to develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures. This role involves verification of complex digital designs that will enhance the Starlink network's capability.

Experience Level

2+ years of experience in design verification and test bench development.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Develop SystemVerilog testbench infrastructure for testing designs.
• Execute test plans, run regressions, and ensure coverage closure.
• Automate test case generation using Python and MATLAB.
• Contribute to pre-silicon verification and post-silicon validation.
• Be a hands-on self-starter for verifying complex designs.

Requirements

Education Requirements

Bachelor’s degree in electrical engineering, computer science, or computer engineering.

Preferred Skills and Experience

• Advanced degree in electrical engineering or computer engineering.
• Experience with UVM verification methodologies.
• Strong object-oriented programming knowledge.
• Experience in constrained random verification.
• Familiarity with scripting languages such as Python for automation.
• RTL design, chip bring-up, and post-silicon validation experience.
• Ability to adapt in a dynamic environment.

Compensation and Benefits

Salary range: Design Verification Engineer/Level I: $120,000 - $145,000 per year; Design Verification Engineer/Level II: $140,000 - $170,000 per year. Comprehensive benefits include medical, vision, and dental coverage, a 401(k) plan, and paid time off including vacation and sick leave.