SOC Design for Test Engineer

Company Overview: Advanced Micro Devices (AMD) is a leader in high-performance computing solutions, dedicated to innovation in AI, data centers, and various computing platforms.

Role Overview

The SOC Design for Test Engineer will oversee the full lifecycle of Design for Testability (DFT) processes, ensuring efficient testing strategies are implemented across various AMD products including servers and gaming devices. This role necessitates collaboration with multiple engineering teams to achieve project objectives effectively.

Experience Level

This is a full-time position intended for candidates with a solid background in electrical or computer engineering, specifically with expertise in DFT practices.

Key Responsibilities

• Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
• Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
• Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
• Apply low power DFT techniques to designs.
• Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
• Analyze test coverage and work on reducing test costs.
• Provide post-silicon support to ensure successful bring-up and improve yield learning.

Required Skills

• Strong understanding of Design For Test methodologies and DFT verification.
• Experience with Tessent TestKompress and Silicon Scan Network (SSN).
• Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
• Exposure to static timing analysis and timing closure processes.
• Experience in pre-silicon test planning, validation, and engagement with design teams.
• Skilled in characterization and debugging of scan/ATPG tests.
• Excellent communication skills and ability to work in global teams.
• Knowledge of low power design concepts such as clock gating and power gating is a plus.

Education Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.