SOC Design for Test Engineer

Company Overview

Advanced Micro Devices (AMD) is a global leader in the semiconductor industry, committed to driving innovation in computing and graphics technologies.

Role Summary

As a SOC Design for Test Engineer at AMD, you will oversee the full Design-for-Test (DFT) lifecycle, from defining specifications to post-silicon support. This position requires collaboration with various engineering teams to develop effective test solutions for a wide range of products.

Experience Level

This position is suitable for candidates with prior experience in DFT methodologies and a strong foundation in electronical engineering principles.

Responsibilities

• Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
• Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
• Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
• Apply low power DFT techniques to designs.
• Achieve DFT timing closure and verify ATPG patterns through gate-level simulations with timing.
• Analyze test coverage and work on reducing test costs.
• Provide post-silicon support to ensure successful bring-up and improve yield learning.

Requirements

• Strong understanding of Design for Test methodologies and DFT verification (e.g., IEEE1500, JTAG 1149.x, scan, memory BIST).
• Experience with Tessent TestKompress and Silicon Scan Network (SSN).
• Proficiency in VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
• Exposure to static timing analysis.
• Experience in pre-silicon test planning and engagement with design teams.
• Skilled in characterization and debugging scan/ATPG tests.
• Ability to analyze part failures for enhanced test coverage and yield.

Education Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.