SOC Design Engineer

Role Summary

An RTL design and integration role in the System on Chip (SoC) design team, where numerous subsystems and IP cores are integrated to produce high-performance SoC products. Responsibilities include SoC level RTL design, block level RTL design, and subsystem level integration targeting applications in networking, security, and storage.

Experience Level

Experienced RTL Designer with a passion for modern digital ASIC design.

Responsibilities

• Develop and maintain SoC and subsystems synthesizable RTL, design methodology, and infrastructure.
• Collaborate directly with IP Architecture, SoC Architecture, and Design Leads.
• Debug and resolve issues with SoC Integration, Design Verification, and post-silicon validation teams.
• Work with IP development and Physical Design teams to meet SoC Power/Performance/Area goals.
• Resolve SoC simulation regression failures in collaboration with SoC Verification Team.
• Support the activities of the Emulation Team.
• Attend and contribute to regular technical status meetings.

Requirements

Experience in RTL (Verilog/System Verilog) ASIC design with implementations targeting leading edge technologies.

• Proven experience with ASIC design tools and synthesis flows.
• Experience executing design checks such as lint, CDC, and LEC.
• Familiarity with industry-standard power flows.
• Proficient in scripting languages like Python, Perl, TCL, Makefile, and csh/bash.
• Skilled in simulation and debugging with functional verification tools including Gate-level simulations.
• Solid understanding of standard bus/interface protocols (AXI, AHB, AMBA).
• Familiarity with networking protocols and encryption protocols.

Education Requirements

Bachelors or Masters degree in Computer/Electrical Engineering.