Silicon Validation Engineer 2

Role Summary

The Silicon Validation Engineer 2 position involves participating in projects within Lattice’s Silicon Engineering team, focusing on validating building blocks in FPGA at the board level to ensure functionality and performance.

Experience Level

2+ years of experience in Silicon Design Validation Engineering.

Responsibilities

• Learn and validate various IPs including SERDES, Memory (DDR4, LPDDR4, DDR5), DPHY, PLL, DSP, Fabric, and I/O.
• Develop validation and characterization plans from silicon arrival to production release.
• Create test logic RTL for intended validation tests.
• Drive new silicon product validation and debug to assess IP functionality and performance.
• Analyze measured data for statistical evaluation and prepare data sheets.
• Act as a central resource with cross-functional teams throughout product development stages.
• Support customer issues post-release as needed.

Requirements

• Bachelor's degree in Electrical Engineering.
• Knowledge of High-Speed Serdes Interface characterization and compliance testing for protocols such as PCIe, Ethernet, and USB.
• Familiarity with high-speed board design and signal integrity evaluation.
• Experience with Verilog/VHDL and FPGA development tools.
• Programming skills in Python or Perl for test automation development.
• Understanding of statistical analysis with tools like JMP or R.
• Experience with characterization equipment such as BERT, VNA, and Oscilloscopes.
• Strong communication skills for cross-functional collaboration.
• Self-motivated with good problem-solving skills.

Education Requirements

Bachelor's degree in Electrical Engineering or related field.