Silicon Design Engineer, RTL design for SoC IPs

Company: Advanced Micro Devices Inc

Location: San Diego, California, United States

Date Posted: 2026-02-08

Role Summary

AMD's Adaptive and Embedded Computing Group (AECG) is looking for a SoC design engineer focused on designing, planning, and executing RTL design for SoC IPs.

Experience Level

Level - Mid-Career

Responsibilities

• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand requirements.
• Help lead and mentor other engineers to achieve project goals and organizational growth.
• Work with verification and physical design teams to achieve high quality design and successful tape outs.
• Design and implement logic functions that enable efficient test and debug.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas during feature development.
• Implement automation to increase design team efficiency.

Requirements

• Must have proven track record of ASIC design on several production tape-outs.
• Experience in designing RTL blocks for an SoC.
• Experience in integrating ASIC IP into an SoC.
• Experience with Arm architecture and APB, AMBA protocols.
• Experience with PCIe transaction layer protocol.
• Experience with synthesis, static timing analysis & optimizations.
• Experience with writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl.
• Experience with using AI tools.
• Ability to develop clear and concise engineering documentation.
• Strong verbal and written communication skills.
• Exhibit strong ownership of tasks and responsibilities.

Education Requirements

Bachelor’s or master’s degree in computer engineering or electrical engineering.