Silicon Design Engineer

Role Overview

We are looking for a motivated and detail-oriented Verification Engineer to join our DDR PHY IP development team. In this entry-level role, your primary focus will be on verifying high-performance DDR PHY intellectual property for advanced SoCs across multiple markets, including data centers, mobile technologies, and automotive systems.

Experience Level

This position is suited for entry-level engineers eager to dive into the world of silicon design and verification.

Key Duties

Your responsibilities will include:

• Developing and maintaining UVM-based verification environments for DDR PHY IP.
• Writing and executing test plans, including directed and constrained-random tests and functional coverage models.
• Debugging simulation failures, analyzing waveforms, and collaborating with RTL designers to resolve issues.
• Creating and maintaining verification collateral such as testbenches, checkers, and scoreboards.
• Performing regression runs, tracking functional coverage, and ensuring full design verification closure.
• Contributing to automation scripts for regression, data analysis, and enhancing verification efficiency.

Job Requirements

To be successful in this role, you should have:

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• A strong understanding of digital design fundamentals, including clocking, timing, and state machines.
• Experience with SystemVerilog and UVM (academic or internship exposure is preferred).
• Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• A basic understanding of DDR memory protocols and PHY architecture is a plus.
• Proficiency in scripting languages like Python, Perl, or TCL for automation.
• Excellent analytical, debugging, and communication skills.
• A keen enthusiasm for learning and solving problems in a collaborative, fast-paced environment.

Education Requirements

A Bachelor’s or Master’s degree in a relevant discipline is preferred.