Silicon Design Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s GPU and Memory System IP, resulting in no bugs in the final design.

Experience Level

Level - Mid-Career

Responsibilities

Key responsibilities include:

• Collaborating with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Building test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Building testbench and developing the Testbench component with UVM.
• Estimating the time required to write the new feature tests and any required changes to the test environment.
• Building directed and random verification tests.
• Debugging test failures to determine the root cause; working with RTL and firmware engineers to resolve design defects and correct any test issues.
• Reviewing functional and code coverage metrics; modifying or adding tests or constraining random tests to meet the coverage requirements.

Requirements

Preferred experience includes:

• Proficiency in IP level or Sub system level verification.
• Proficiency in debugging firmware and RTL code using simulation tools.
• Proficiency in using UVM Methodology and testbenches.
• Experience with Verilog, System Verilog, SVA, C, and C++.
• Development of UVM based verification frameworks and testbenches, processes, and flows.
• Good understanding and hands-on experience in UVM concepts and SystemVerilog language.
• Good knowledge of DMA, Memory system, Cache.
• Exposure to leadership or mentorship is an asset.
• Hands-on working experience and knowledge of formal verification is preferred and will be considered a valuable asset.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.

Education Requirements

Bachelor's or Master's degree with good experience in Computer Engineering/Electrical Engineering.