Silicon Design Engineer

Role Summary

The Control Fabric (CF) IP is crucial for AMD's System-on-Chip (SoC) designs. This role involves working with cutting-edge technologies, including network-on-chip (NoC), chiplet interconnects, remote system management units, and more. The role is located in Shanghai, China, and is part of the global CF team.

Experience Level

Mid-Career

Responsibilities

• Understand IP features at the system level and collect relevant knowledge.
• Develop comprehensive block-level verification test plans for design under test (DUT).
• Develop testbenches and test cases using SystemVerilog, UVM, and formal verification methodologies.
• Create reusable verification IP for different verification levels.
• Support subsystem and SoC-level verification and enable IP in SoCs.

Requirements

• Education Requirements: Master's degree in Electrical Engineering, Computer Science, or a related field.
• Minimum of 5 years of relevant work experience.

The candidate should possess excellent knowledge of design verification methodologies, including System Verilog, UVM, and formal coding tools. Strong communication skills and fluency in English are mandatory.