SerDes Verification Engineer

Role Overview

This position involves verification and validation for high-speed SerDes interfaces, with a focus on ensuring data integrity, performance, and compliance with protocols. You will collaborate with design and hardware teams to maintain quality standards.

Role Summary

The SerDes Verification Engineer focuses on developing verification plans and executing tests for SerDes IPs and subsystems. This includes ensuring designs meet functional and performance specifications while performing simulations and debug issues in the design process.

Experience Level

This role is suited for individuals with significant experience in SerDes verification or high-speed communication verification, preferably with a hands-on background in relevant methodologies and protocols.

Responsibilities

• Develop and execute verification plans and testbenches for SerDes IPs.
• Design and implement verification testbenches using methodologies like UVM and SystemVerilog.
• Perform simulations and analyze results to debug various design issues.
• Evaluate SerDes performance metrics such as jitter, bit error rates, and signal integrity.
• Conduct protocol compliance testing against established standards such as PCIe and USB.
• Create automated regression tests for design robustness across iterations.
• Collaborate with design teams to resolve issues and implement verification changes.
• Document verification results and process improvements.

Requirements

• Experience with high-speed communication verification and protocols.
• Hands-on proficiency in UVM, SystemVerilog, or similar tools.
• Knowledge of high-speed serial protocols like DDR, PCIe, and UCIe.
• Understanding of hardware description languages such as VHDL or Verilog.
• Strong analytical and debugging skills.
• Experience with DDR protocols for memory interfaces.

Education Requirements

Preferred education includes a degree in Electrical Engineering or a related field, with experience in integrated circuit design and verification.