SerDes Verification Engineer

Role Summary

As a SerDes Verification Engineer, you will be responsible for the verification and validation of high-speed SerDes interfaces, ensuring the systems meet data integrity, performance, and protocol compliance standards. This involves close collaboration with hardware and design teams to align SerDes designs with specified requirements.

Experience Level

Level - Mid-Career

Responsibilities

Key responsibilities include:

• Develop and execute verification plans and testbenches for SerDes IPs.
• Design and implement verification testbenches using methodologies such as UVM, SystemVerilog, and VHDL.
• Perform simulations, analyze results, and debug issues in SerDes blocks.
• Evaluate performance characteristics including jitter, bit error rates, and signal integrity.
• Verify protocol compliance for SerDes protocols like UCIe, PCIe, and others.
• Develop automated regression tests for design robustness.
• Collaborate with design and software teams on issues and design changes.
• Create detailed reports and documentation of verification results.
• Provide feedback for improvements in design and verification methodologies.

Requirements

Candidates must have:

• Experience in SerDes verification or high-speed communication verification.
• Strong experience with verification methodologies like UVM and SystemVerilog.
• Knowledge of high-speed serial protocols (UCIe, PCIe, etc.).
• Ability to analyze and interpret signal integrity issues.
• Familiarity with HDL languages such as VHDL or Verilog.

Education Requirements

Relevant degree in engineering or a related field is preferred.