Senior Staff Verification Engineer

Job Title

Senior Staff Verification Engineer

Role Summary

The Senior Staff Verification Engineer is responsible for leading verification projects in the ASIC Digital Design domain. The role involves collaborating with cross-functional teams to ensure quality and reliability of designs.

Experience Level

This position is suited for Mid-Career professionals with significant experience in ASIC verification and related areas.

Responsibilities

• Lead verification efforts for complex ASIC designs.
• Collaborate with design engineers to validate logic designs and ensure all specifications are met.
• Develop and enhance verification methodologies and processes.
• Mentor junior engineers and provide technical guidance.
• Identify and implement improvements to existing verification processes.

Requirements

• Proven experience in ASIC verification, with a strong background in verification methodologies such as UVM or SystemVerilog.
• Experience with simulation tools and environments.
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration abilities.
• Ability to work effectively in a team-oriented environment.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. An advanced degree is preferred.