Senior SoC Integration Engineer

Role Overview

The Senior SoC Integration Engineer will play a crucial role within the SoC Physical Integration team, collaborating with various engineering disciplines to ensure the successful physical and electrical verification of AMD's SoC FPGA/ACAP devices. This position requires interaction with teams across different geographical locations and performing significant tasks pivotal for product advancement.

Position Summary

Your primary responsibilities will revolve around defining integration methodologies, verifying chip-level designs, and executing electrical verifications. You will also focus on developing tools that enhance design efficiency and coordinating with design teams for smooth integration processes.

Experience Level

This is a mid-career position aimed at individuals with a solid foundation in FPGA architecture and related design tools.

Key Responsibilities

• Define and develop flows and methodologies for chip level integration.
• Create tools for enhancing design verification and efficiency.
• Design and verify FPGA/ACAP sub-blocks (both RTL and custom).
• Coordinate activities among different design groups to ensure effective integration.
• Perform chip level physical verification and electrical verification.

Necessary Qualifications

• Basic understanding of FPGA architecture.
• Experience with design and verification tools such as Virtuoso and Calibre.
• Familiarity with Place and Route (P&R) tools.
• Solid circuit design knowledge with simulation experience using Spice and Verilog.
• Proficiency in scripting languages including Perl, Python, TCL, and C-shell.
• Strong debugging capabilities.
• Experience with basic Unix data management and job control.
• Excellent written and oral communication skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering with hands-on FPGA experience.