Senior SOC/ASIC DFT Engineer

Role Summary

We are seeking a motivated and proactive engineer to join our Silicon Engineering team. You will be responsible for designing and implementing innovative ASICs that will enhance connectivity for our ambitious satellite communications project, Starlink. This position requires collaboration with cross-disciplinary teams to help deliver high-quality solutions for complex systems.

Experience Level

This position is classified as Mid-Career, requiring 5+ years of relevant industry experience in semiconductor Design For Test (DFT) engineering and post-silicon validation.

Responsibilities

• Implement and optimize DFT architectures using Siemens Tessent tools.
• Integrate and verify DFT IPs within subsystems.
• Set up and run ATPG tools and methodologies for various test models, focusing on compression and diagnosis.
• Create and validate DFT patterns for post-silicon bring-up and assist with ATE debug through silicon characterization cycles.
• Develop test scripts and automate processes using languages such as Perl, Python, Tcl, or C++.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or physics is required. Candidates must have at least 5 years of experience in semiconductor DFT engineering, including post-silicon validation or production testing.

Education Requirements

A Bachelor’s degree in electrical engineering, computer engineering, or physics is required. A Master’s or PhD in a related field is preferred.