Senior Engineer, IO Layout Design

Role Summary

The Senior Engineer in IO Layout Design will be responsible for designing and developing advanced physical IP for semiconductor applications. This role requires a deep understanding of semiconductor device physics, digital design, and effective collaboration with diverse global teams.

Experience Level

This position is suited for an individual with a strong background in layout design and semiconductor technology, with a focus on CMOS fundamentals and scripting languages.

Responsibilities

• Design and develop physical IP such as SERDES, DDR, and Memory.
• Collaborate globally to implement and optimize layout designs.
• Utilize CMOS fundamentals to enhance design processes.
• Employ scripting (Unix/Shell/Python/TCL) to automate design workflows.
• Conduct design reviews and provide detailed feedback.
• Stay abreast of industry trends for cutting-edge design advancements.

Requirements

• Proven understanding of semiconductor device physics and digital design principles.
• Solid foundation in CMOS fundamentals and layout design.
• Experience with Unix/Shell scripting; familiarity with Python/TCL preferred.
• Effective communication and team collaboration skills.

Education Requirements

A degree in Electrical Engineering or a related field is required.