Senior Digital Verification Engineer

Role Summary

The Senior Digital Verification Engineer at Synopsys will focus on developing and verifying high-speed PHY IPs in dynamic project environments. The role involves detailed functional verification, problem-solving, and collaboration with engineering teams to ensure product quality and innovation in silicon capabilities.

Experience Level

This position requires a Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or a Master’s degree with 2-6 years. Experience in pre-silicon verification of complex ASIC, PHY, or SoC designs is essential.

Responsibilities

• Develop robust functional verification environments (test benches) for high-speed PHY IPs.
• Create comprehensive test plans and detailed test cases for coverage.
• Implement checkers, assertions, and test generators.
• Execute simulations and perform coverage analysis.
• Collaborate with engineering teams to resolve issues and optimize strategies.
• Contribute to process improvements and knowledge sharing.

Requirements

• Solid background in pre-silicon verification, Verilog, System Verilog, and UVM.
• Proficiency with development and verification tools, strong diagnostic skills.
• Preferred experience in formal verification, scripting languages, and high-speed protocol knowledge.
• Detail-oriented with a proactive approach to problem-solving.
• Excellent communication skills and ability to work in diverse teams.

Education Requirements

Bachelor's degree in Electronics Engineering, or equivalent, with relevant work experience.