Senior DFT Architect

Role Overview

The Circuit Technology team seeks a skilled DFT Methodology Architect/RTL Execution Lead for high-speed SERDES PHY, next-generation memory PHY, and die-to-die interconnect IPs. The role involves defining the DFX architecture, RTL coding, supporting scan stitching, and timing constraints development, and aiding in post-silicon bring-up.

Experience Level

This position is ideal for mid-career professionals with substantial industry experience in DFT techniques, RTL development, and silicon testing methodologies.

Responsibilities

• Lead the definition of PHY-specific Design for Test/Debug/Yield features.
• Implement DFX features in RTL utilizing Verilog.
• Understand and apply DFX architectures and micro-architectures.
• Engage with JTAG standards and at-speed scan testing implementation.
• Conduct gate-level simulations using Synopsys VCS and Verdi.
• Perform Spyglass bring-up and analysis to identify test coverage gaps.
• Plan, implement, and verify MBIST (Memory Built-In Self-Test).
• Support planning, patterns, and debug with Test Engineering.
• Facilitate silicon bring-up and debugging processes.
• Develop efficient DFx methodologies compatible with front-end and physical design flows.

Requirements

Candidates must possess strong analytical skills, attention to detail, and the capacity for independent task management. Proven experience in design for test methodologies and RTL coding is essential.

Education Requirements

A BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, complemented by industry experience in advanced DFT techniques.